Tuesday, June 26, 2007

General about Hypertransport Technology

HyperTransport provides a point-to-point interconnect that can be extended to support a wide range of devices. HyperTransport provides a high-speed, high-performance, point-to-point dual simplex link for interconnecting IC components on a PCB. Data is transmitted from one device to another across the link.

The width of the link along with the clock frequency at which data is transferred are scalable:

  • Link width ranges from 2 bits to 32-bits

  • Clock Frequency ranges from 200MHz to 800MHz (and 1GHz in the future)

This scalability allows for a wide range of link performance and potential applications with bandwidths ranging from 200MB/s to 12.8GB/s.

At the current revision of the spec, 1.04, there is no support for connectors implying that all HyperTransport (HT) devices are soldered onto the motherboard. HyperTransport is technically an "inside-the-box" bus. In reality, connectors have been designed for systems that require board to board connections, and where analyzer interfaces are desired for debug.

Transfer Types Supported

HT supports two types of addressing semantics:

  1. legacy PC, address-based semantics

  2. messaging semantics common to networking environments

Address-Based Semantics

The HT bus was initially implemented as a PC compatible solution that by definition uses Address-based semantics. This includes a 40-bit, or 1 Terabye (TB) address space. Transactions specify locations within this address space that are to be read from or written to.

HyperTransport does not contain dedicated I/O address space. Instead, CPU I/O space is mapped to high memory address range (FD_FC00_0000h—FD_FDFF_FFFFh). Each HyperTransport device is configured at initialization time by the boot ROM configuration software to respond to a range of memory address spaces. The devices are assigned addresses via the base address registers contained in the configuration register header. Note that these registers are based on the PCI Configuration registers, and are also mapped to memory space (FD_FE00_0000h—FD_FFFF_FFFFh. Unlike the PCI bus, there is no dedicated configuration address space.

Read and write request command packets contain a 40-bit address Addr[39:2]. Additional memory address ranges are used for interrupt signaling and system management messages. Details regarding the use of each range of address space is discussed in subsequent chapters that cover the related topic.

Data Transfer Type and Transaction Flow

The HT architecture supports several methods of data transfer between devices, including:

  • Programmed I/O

  • DMA

  • Peer-to-peer

Programmed I/O Transfers

Transfers that originate as a result of executing code on the host CPU are called programmed I/O transfers. For example, a device driver for a given HT device might execute a read transaction to check its device status.

DMA Transfers

HT devices may wish to perform a direct memory access (DMA) by simply initiating a read or write transfer.

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