Tuesday, June 26, 2007

Link Initialization in the CPU

The process of initializing each link begins during cold reset. The complete link initialization process consists of several stages:

  1. Low-level link initialization — This hardware mechanism ensures that the devices attached to a link can pass transactions safely in both directions following a cold reset. This includes:

    • Determining the link width that can be used after cold reset. This width is based on the maximum width of the smallest transmitter or receiver, but limited to 8 bits.

    • Establishing the default clock frequency of 200 MHz for all devices.

    • Synchronizing the transmit and receive clocks and setting up the receive FIFOs with the appropriate load and unload values.

    • Establishing the reference point for the beginning of packet transmission in both directions. This reference defines the beginning of 4-byte aligned packet transmission as well as the beginning of the CRC window.

  2. The next stage of link initialization occurs after cold reset and is driven primarily by system firmware. This stage is needed because the low-level link initialization does not guarantee that the link is operating at maximum clock frequency and link width. The process involves:

    • Reading the maximum link-width fields from the Link Configuration register and loading the link-width control registers with the maximum common width (done for both upstream & downstream directions of a link).

    • Reading the Link Frequency Capability registers and loading the maximum common frequency into the Link Frequency control registers (done for both upstream and downstream directions).

    • Initiating a warm reset (or LDTSTOP# disconnect/connect sequence) to force the updated values to take effect.

Low-Level Link Width Initialization

Low-Level initialization of the link width is performed as a hardware sequenced point-to-point handshake between the two devices attached to each link. Once completed, the devices at each end of the link will be ready to perform transactions using either 2-, 4-, or 8-bits. This link-width negotiation sequence may not result in links operating at their maximum width. For example, since the maximum width following the negotiation is 8 bits, 16-bit, 32-bit, and asymmetrically-sized operations are not possible until enabled by software, which is the second stage of link-width initialization.

Determining Low-Level Link Width

HT permits devices with different link widths to be directly connected. This results in unused receiver and transmitter pins on the wider device. Logic within a device of course has no knowledge of the width of devices to which it connects. Consequently, a hardware handshake process is defined at powerup to ensure that all devices can determine a safe link width over which devices can communicate.

  • The transmitter width can be wider than the receiver, thus the values listed in column 2, are shown to be 32 bits wide (maximum possible width).

  • The receiver width may be wider than the transmitter width. In this event, the transmitter cannot report the correct receiver size and is required to drive all CAD lines to 1's.

  • Rows 3 and 4 list the transmit values for specifying 8-bit and 16-bit receiver widths, respectively. Note that transmit values seem to represent receiver widths that are much wider than the actual receiver size. (i.e., 32 bits of all 1's reflect a receiver width of 4 bytes). However, because the low-level link initialization process limits the maximum link width to CAD[7:0], a value beyond FFh has no meaning. The upper lines are driven to ensure backward compatibility with the early versions of LDT.

  • Row 5 defines the transmit value for a 32-bit receiver width. While this value seems to define precisely a 32-bit receiver width, the low-level receiver width is limited to FFh as described in the previous bullet.

During reset both devices deliver a pattern that represents the size of their receiver .

  • The 8-bit link delivers a value of FFh (logic doesn't know the receiver on the other end of the link is only 4-bits wide).

  • The 4-bit link delivers a value of Fh.

The receivers then detect the pattern driven, and each device learns the link width to use when transmitting packets to the other.

  • The 4-bit link device sees only Fh on CAD[3:0], and interprets the size of the remote receiver to be 4-bits wide.

  • The 8-bit link device has its CAD[7:4] pins tied to differential logic 0 and detects the value Fh on CAD[3:0], and also interprets the size of the remote receiver to be 4-bits wide.

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