System Management Transactions for HT Cpu

HT provides a message passing mechanism between the Host Bridge and the System Management Controller (SMC). One of the primary purposes of HT messages is to eliminate dedicated pins and traces that would otherwise be required to signal various events, reducing pin count and cost. These System Management (SM) messages are delivered via packets that support a wide variety of functions including:

• HT Power Management

• X86 Power Management

• X86 Legacy CPU Signalling (e.g. A20M, FERR#, and IGNNE#)

HT System Management messages in conjunction with LDTSTOP# may be used to support operations such as changes in operating frequency and link width, or to disable the links to save power. It is also through System Management (SM) requests that many of the x86 compatibility mechanisms are accomplished as indicated above. Further, x86 platforms are required to support SM and LDTSTOP# for power management. Power Management support for HT devices is optional in non-x86 platforms; however, many non-x86 systems do support power management. Note also that the specification requires all HT devices to forward SM packets in both directions.

Sources of SM Request

System Management requests may be either sent in the upstream or downstream direction, All SM requests moving upstream originate at the System Management Controller (SMC) and downstream requests originate at the Host Bridge. Note that the SMC typically resides in the south bridge (or I/O Controller Hub) where the legacy signals typically originate and where power management registers reside.

System Management Address Range

System Management transactions are recognized by their assigned address range. The HT specification reserves a 1MB address range for system management transactions from FD_F910_0000h to FD_F91F_FFFFh. In reality, only the upper address bits are needed to identify that the transaction falls within the assigned 1MB range. SM request packets include only the upper 20 bits (A39:A20) of the HT address for identifying the SM range (FD_F91h). Note that the lower 5 nibbles (or 20 bits) of the address are not defined and could theoretically be any value between 0_0000h and F_FFFF. The 1MB block of SM address space serves only to identify SM transactions and does not actually target any memory locations.

The SMC & Upstream Request Packets

The System Management Controller generates SM requests in response to both software initiated events (i.e., writes to registers within the south bridge) and hardware events (e.g. inactivity timeouts).