Tuesday, June 26, 2007

HyperTransport Configuration Space Format

This section describes the general format of the configuration space used by a HyperTransport functional device. The discussion here focuses on two major areas:

  • How a HyperTransport device is similar and different from a PCI device in its use of the generic header region of configuration space.

  • The use of the required and optional HyperTransport advanced capability register blocks also located in the required 256 byte configuration space.

Two Header Formats Are Used

The first one fourth (16 dwords) of any PCI configuration space is called the header. As in the case of PCI devices, HyperTransport devices use two header formats: one for HT-to-HT bridges, called header type 1, and the other for all non-bridge devices (including tunnels and single link end (cave) devices) called header type 0. The lower bits in the Header Type field within both types of PCI configuration header is hard coded with the type code; software checks this field early in the process of device discovery to determine which of the header formats it is dealing with.

The Type 0 Header Format

Basic PCI functionality is managed by having BIOS or other low level software read certain hard-coded header fields to obtain device requirements, then having it program other fields to set up plug-and-play options.

PCI Advanced Capability Registers

While many early PCI devices were managed using just the register fields in the configuration space header, many additional features have been added over the years which require dedicated registers to manage them. For these devices which have capabilities beyond basic PCI compliance, the generic PCI header registers are augmented by one or more additional register sets outside of the header area, but still within the 256 byte PCI configuration space. PCI calls these advanced capability register blocks;

Many Advanced Capabilities Are Defined

Under the current PCI specification, advanced capability block register sets have been defined for all sorts of purposes. Two important classes are:

  • Register sets for bus extensions such as HyperTransport, PCI-X, and AGP.

  • Register sets for enhanced device management, including Message Signalled Interrupts (MSI), Power Management, Vital Product Data, etc.

When a PCI compatible device is designed, the basic PCI configuration space type 0 or type 1 header fields are implemented as are any additional advanced capability register blocks which may be needed. The format of an advanced capability block varies with the type, and a Capability ID byte at the start of each block identifies which type it is; the capability ID for HyperTransport is 08. At a minimum, a HyperTransport device must implement the 256 byte PCI configuration space memory, containing a header AND at least one HyperTransport advanced capability block (Host/Secondary or Slave/Primary Interface Block).

Discovering The Advanced Capability Blocks

If a PCI compatible device implements advanced capability blocks, low-level software must find and configure each one. Because the specific location of advanced capability blocks within the 256 byte configuration space is not specified, they must be "discovered" by executing some variation of the following software configuration process

  1. Use the capability pointer (CapPtr) at dword 13 in the header to determine the configuration space offset (from the beginning of configuration space) to the first advanced capability register block. Check the first byte in the block to determine the capability ID (HT = 08).

  2. Next, check the upper byte in the first dword to determine the HyperTransport capability block Type. HyperTransport supports a number of these: Host/Secondary, Slave/Primary, Interrupt Discovery & Configuration, etc.

  3. Set up all of the registers in the capability block using configuration cycles.

  4. Use the next pointer (NPtr) contained in the second byte of the first advanced capability block to determine the offset (from the beginning of configuration space) to the next capability block in the "linked list". If the ID field is "08", this is another HyperTransport capability block. Read the Type field, and set up the register fields as appropriate.

  5. Continue the discovery and set up process until the last capability block has been located and set up. If a block is the last one, its Nptr field is zero — indicating the end of the linked list of advanced capability blocks.

Refer to MindShare's PCI System Architecture, 4th Ed. book for a complete description of configuration space advanced capability management.

HyperTransport Configuration Type 0 Header Fields

In this section, the configuration header format for non-bridge HyperTransport devices (type 0 header format) is described. For the most part, HyperTransport devices use these fields in the same way as PCI devices; the few differences are described here. Header fields not mentioned are used in the same way as in PCI devices.

Header Command Register

the command register occupies the lower 16 bits at dword 01. The header Command register is used by BIOS or other software to enable basic capabilities of the device on the primary bus, including bus mastering, target address decoding, error response capability, etc.

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