Tuesday, June 26, 2007

What HT Brings

What HT Brings

HyperTransport is a point-to-point, high-performance, "inside-the-box" motherboard interconnect bus. It targets IT, Telecom, and other applications requiring high bandwidth, scalability, and low latency access.

Key Features Of HyperTransport Protocol

The key characteristics of the HT technology include:

  • Open architecture, non-proprietary bus

  • One or more fast, point-to-point links

  • Scaling of individual link width and clock speed to suit cost/performance targets

  • Split-transaction protocol eliminates retries, disconnects, and wait-states.

  • Standard and optional isochronous traffic support

  • PCI compatible; designed for minimal impact on OS and driver software

  • CRC error generation and checking

  • Programmable error handling strategy for CRC, protocol, and other errors

  • Message signalled interrupts

  • System Management features

  • Support for bridges to legacy busses

  • x86 compatibility features

  • Device types including tunnels, bridges, and end devices permit construction of a system fabric comprised of independent, customized links.

Formerly known as AMD's Lightning Data Transport (LDT), HyperTransport is backed by a consortium of developers.

The Cost Factor

In addition to technology-related issues, there is always pressure on the platform designer to increase performance and other capabilities with each new generation, but to do so at a lower cost than the previous one. One popular method of measuring the success of this effort is to compare the bandwidth of one I/O bus to another, and the number of signals required to achieve it. This bandwidth-per-pin comparison works fairly well because I/O bus bandwidth is a critical factor in determining if system data bottlenecks exist, and a lower pin count translates directly into cost savings due to smaller IC packages, lower power, simplified motherboard routing, etc.

An example:

The bandwidth-per-pin for a generic 32-bit PCI bus during a burst transfer is approximately 3.5 MB/s (132 MB/s [33MHz x 4 bytes]/38 pins [32 data signals + 5 control lines + 1 clock]). By comparison, a 32 bit HyperTransport interface running at the lowest clock speed of 200MHz yields a per-pin burst bandwidth of approximately 22 MB/s (1600 MB/s [200Mhz x 2 DDR x 4 bytes]/74 pins [32 CAD signal pairs + 4 clock pairs + 1 CTL pair]).

Networking Support

Finally, at the time of the writing of this book, the HyperTransport I/O Link Specification is at revision 1.04. This specification revision mainly targets I/O subsystem improvements in conventional desktop and server platforms.

A growing number of applications require architectures that integrate well with networking environments. In many of these systems, unlike desktops and servers, processing may be decentralized and features such as message streaming, peer-peer transfers, and assigned isochronous bandwidth become important. In addition, device types such as switches help in building topologies suited to communications networking. To accommodate networking applications, work is well underway on the 1.05 and 1.1 revisions of the HyperTransport I/O Link Specification. The 1.05 specification includes the HyperTransport switch specification and the 1.1 specification incorporates the networking extensions specification.

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